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Macros</h2></td></tr>
<tr class="memitem:gaebbb18b57a2957ab4a90b54c4f557fea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaebbb18b57a2957ab4a90b54c4f557fea">XAXIVDMA_MISMATCH_ERROR</a>&#160;&#160;&#160;0x80000010</td></tr>
<tr class="separator:gaebbb18b57a2957ab4a90b54c4f557fea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf573ed8e7f474ba68daa5e8070b976a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaf573ed8e7f474ba68daa5e8070b976a0">XAxiVdma_ReadReg</a>(BaseAddress,  RegOffset)                      &#160;&#160;&#160;XAxiVdma_In32((BaseAddress) + (RegOffset))</td></tr>
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<tr class="memitem:gaaa7bae0ada2e94f563704a8ae4cabfde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#gaaa7bae0ada2e94f563704a8ae4cabfde">XAxiVdma_WriteReg</a>(BaseAddress,  RegOffset,  Data)                &#160;&#160;&#160;XAxiVdma_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor Alignment</div></td></tr>
<tr class="memitem:ga74cbf8945ca6cf9175bac9d7ad21a1bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__axivdma__v6__0.html#ga74cbf8945ca6cf9175bac9d7ad21a1bf">XAXIVDMA_MAX_FRAMESTORE</a>&#160;&#160;&#160;32</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Maximum transfer length</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This is determined by hardware </p>
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<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets on TX (Read) and RX (Write) channels are identical</p>
<p>The version register is shared by both channels </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Start Addresses Register Array for a Channel</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Base offset is set in each channel This set of registers are write only, they can be read when C_ENABLE_VIDPRMTR_READS is 1. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of the XAXIVDMA_CR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks of the XAXIVDMA_SR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for interrupts</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and shift for delay and coalesce</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for the XAXIVDMA_CDESC_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_TDESC_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_FRMSTORE_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_PARKPTR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_VERSION_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask for XAXIVDMA_S2MM_IRQ_MASK_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Frame Delay shared by start address registers and BDs</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Buffer Descriptor offsets</div></td></tr>
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